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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . v g a p w m c o n t r o l l e r w i t h d i f f e r e n t i a l v o l t a g e f e e d b a c k a p w 8 7 2 8 f e a t u r e s g e n e r a l d e s c r i p t i o n adjustable output voltage from +0.6v to +3.3v - 0 . 6 v r e f e r e n c e v o l t a g e - 0.6% accuracy over-temperature operates from an input battery voltage range of +1.8v to +28v remote feedback sense for excellent output voltage refin function for over-clocking purpose from 0.5v~2.5v range power-on-reset monitoring on vcc pin excellent line and load transient responses pfm mode for increased light load efficiency programmable pwm frequency from 100khz to 500khz selectable forced pwm or automatic pfm/pwm mode built in 30a output current driving capability integrate mosfet drivers integrated bootstrap forward p-ch mosfet adjustable integrated soft-start and soft-stop power good monitoring 70% under-voltage protection 125% over-voltage protection tqfn3x3-16 package lead free and green devices available (rohs compliant) a p p l i c a t i o n s notebook table pc hand-held portable aio pc the APW8728 is a single-phase, constant on-time, synchronous pwm controller, which drives n-channel mosfets. the APW8728 steps down high voltage to generate low-voltage chipset or ram supplies in notebook computers. the APW8728 provides excellent transient response and accurate dc voltage output in either pfm or pwm mode. in pulse frequency mode (pfm), the APW8728 provides very high efficiency over light to heavy loads with loading- modulated switching frequencies. in pwm mode, the converter works nearly at constant frequency for low-noise requirements. APW8728 is built in remote sense function for applications that require remote sense. the APW8728 is equipped with accurate positive current limit, output under-voltage, and output over-voltage protections, perfect for nb applications. the power-on- reset function monitors the voltage on vcc to prevent wrong operation during power-on. the APW8728 has a 1ms digital soft start and built-in an integrated output discharge device for soft stop. an internal integrated soft- start ramps up the output voltage with programmable slew rate to reduce the start-up current. a soft-stop function actively discharges the output capacitors. the APW8728 is available in 16pin tqfn3x3-16 package respectively. s i m p l i f i e d a p p l i c a t i o n c i r c u i t v out l q 1 q 2 refin apw 8728 v in rtn vout pok v cc = 5 v phase ugate lgate r pok en ocset ton r ton
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 p i n c o n f i g u r a t i o n o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . tqfn 3 x 3 - 16 ( top view ) v o u t v c c f b p o k r e f i n g n d l g a t e t o n e n r t n b o o t u g a t e p h a s e o c s e t p v c c 1 8 7 6 5 4 3 2 9 10 11 12 1 3 1 4 1 5 1 6 p g n d handling code temperature range . package code apw 8728 qb : assembly meterial xxxxx xxxxx - date code apw 8728 apw 8728 package code temperature range i : - 40 to 85 o c handling code assembly meterial g : halogen and lead free device qb : tqfn 3 x 3 - 16 tr : tape & reel l : lead free device
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 3 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) - 0.3 ~ 7 v v boot - gnd boot supply voltage (boot to gnd or pgnd ) - 0.3 ~ 3 7 v v boot boot supply voltage (boot to phase) - 0.3 ~ 7 v all other pins (vout, ton, en and fb to gnd) - 0.3 ~ v cc +0. 3 v ugate voltage (ugate to phase) < 20 ns p ulse w idth > 20 ns p ulse w idth - 5 ~ v boot + 1.5 - 0.3 ~ v boot +0.3 v lgate voltage (lgate to gnd) < 20 ns p ulse w i dth > 20 ns p ulse w idth - 5 ~ v cc + 1.5 - 0.3 ~ v cc +0.3 v v phase phase voltage (phase to gnd) < 20 ns p ulse w idth > 20 ns p ulse w idth - 5 ~ 35 - 1 ~ 30 v t j ma ximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature(10 seconds) 260 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2 ) tqfn3x3 - 16 40 c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. symbol parameter range unit v in converter input voltage 1.8 ~ 28 v v cc vcc supply voltage 4.5 ~ 5.5 v v out converter output voltage (external refin input) 0.5 ~ 2.5 v converter output voltage (internal fb setting) 0.6~ 3.3 v i out converter output cur rent 0 ~ 30 a t j junction temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) note 3: refer to the typical application circuit.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s APW8728 symbol parameter test condition s min. typ. max. unit v out and v fb v oltage external refin o utput voltage tolerance, refin=1v - 5 - 5 mv refin voltage external refin a djustable output range 0.5 - 2.5 output voltage internal fb a djustab le output range 0.6 - 3.3 v reference voltage 0.6 v t a = 25 o c - 0.4 - +0.4 % v ref regulation accuracy t a = - 40 o c ~ 85 o c - 0.6 - +0.6 % i fb fb input bias current fb=0.5v 0.02 0.1 m a t dis v out d ischarge resistance - 20 32 w supply current i vcc vcc input bias current vcc current, en=5v, vfb=0.65v, phase=0.5v 600 750 m a i vcc_shdn vcc shutdown current en =gnd, vcc=5v - 0 7 m a switching frequency and duty and i nternal s oft s tart t on on time v in =15v, v out =1.25v, r ton =1m w 267 334 401 ns t on (min) minimum on time 80 110 140 ns t off (min) minimum off time v fb =0.55v, v phase = - 0.1v 350 450 550 ns t ss internal s oft s tart t ime en high to v out regu lation(95%) - 1.0 - ms gate driver ug pull - u p resistance boot - ug=0.5v - 1.5 3 w ug sink resistance ug - phase=0.5v - 0.7 1.8 w l g pull - up resistance pvcc - lg=0.5v - 1.0 2.2 w l g sink resistance lg - pgnd=0.5v - 0.5 1.2 w ug to lg dead time (note4) ug falling to lg rising - 20 - ns lg to ug dead time (note4) lg falling to ug rising - 20 - ns bootstrap switch v f ron v vcc ? v boot - gnd , i f = 10ma - 0.3 0.4 v i r reverse leakage v boot - gnd = 30v, v phase = 25v, v vcc = 5v - - 0.5 m a vcc por threshold v vcc_thr ris ing vcc por threshold voltage 4.25 4. 35 4.45 v vcc por hysteresis - 100 - mv v pvcc_thr ris ing p vcc por threshold voltage 4.25 4.35 4.45 v pvcc por hysteresis - 100 - mv u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 5 v a n d t a = - 4 0 t o 8 5 o c . t y p i c a l v a l u e s a r e a t t a = 2 5 o c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 5 e l e c t r i c a l c h a r a c t e r i s t i c s APW8728 symbol parameter test condition s min. typ. max. unit control inputs shutdown - - 0.4 external reference, v out =v refin 0.5 - 2.5 refin voltage threshold in ternal reference, v out = fb setting 2.8 3 3.2 v refin leakage refin =0v - 0.1 1 .0 m a refin slew rate internal rise/fall limit - 8 - mv/us shutdown - - 0.4 v hysteresis - 30 - mv en voltage threshold enable 0.5 - - v power - ok indicator pok in from lower (pok goes high) 87 90 93 % v pok pok threshold pok out from normal (pok goes low) with 30us noise filter 120 125 130 % i pok p ok leakage current v pok =5v - 0.1 1.0 m a p ok sink current v pok =0.5v 2.5 7.5 - ma pok enable delay time en high to pok high - 1.6 - ms current sense i ocset i ocset ocp threshold i ocset sourc ing 18 20 22 a t ci ocset i ocset t emperature c oefficient on t he b asis of 25c - 4500 - ppm/ o c v ocset current l imit t hreshold s etting r ange v ocset - gnd voltage, over a ll t emperature 30 300 mv maximum current l imit t hreshold r ocset open - 0.6 v zero c ro ssing c omparator o ffset v gnd - phase voltage - 3 0 3 mv over current protection c omparator o ffset (v ocset - phase - v gnd - phase ) voltage, v ocset - gnd =60mv - 10 0 10 mv protection v uv uvp threshold 60 70 80 % uvp debounce interval - 16 - m s uvp enable delay en high to pok high - 1.6 - ms u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 5 v a n d t a = - 4 0 t o 8 5 o c . t y p i c a l v a l u e s a r e a t t a = 2 5 o c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 6 e l e c t r i c a l c h a r a c t e r i s t i c s APW8728 symbol parameter test condition s min. typ. max. unit protection v ovr ovp rising threshold 120 125 130 % ovp hysteresis - 5 - % ovp propagation delay v fb rising - 2 - m s t otr otp rising threshold (note 4) - 140 - o c otp hyste r esis (note 4) - 25 - o c remote sense amplifier bw open loop bandwidth (note4) - 6 - mhz open loop gain (note4) - 86 - db u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 5 v a n d t a = - 4 0 t o 8 5 o c . t y p i c a l v a l u e s a r e a t t a = 2 5 o c . note4: guaranteed by design.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 7 p i n d e s c r i p t i o n pin no. tqfn3x3 - 16 name function 1 vout this pin is the positive node of the differential remote voltage sensing. the vout pin should be connected to the remote load voltage sense point directly. 2 vcc supply v oltage i nput p in for c ontrol c ircuitry . connect +5v from the vcc pin to the gnd. decoupling at least 1 m f of a mlcc capacitor from the vcc pin to the gnd. 3 fb output v oltage f eedback p in. in internal mode, t his pin is connected to the resistive divider that set the desired output voltage. the p ok , uvp, and ovp circuits detect this signal to report output voltage status. 4 pok power good output. po k i s a n o pen d rain o utput used to in dicate the status of the output voltage. connect the pok in to +5v through a pull - high resistor. 5 refin enable/shutdown pin or external reference selection of the pwm control ler. 6 gnd signal g round for t he ic 7 pgnd power ground of the lg low - side mosfet driver. connect the pin to the source of the low - side mosfet 8 lgate output of the low - side mosfet driver. connect this pin to gate of the low - side mosfet. swings from pgn d to vcc. 9 pvcc supply voltage input pin for the lg low - side mosfet gate driver. connect +5v from the pvcc pin to the pgnd pin. decoupling at least 1 m f of a mlcc capacitor from the pvcc pin to the pgnd pin. 10 ocset current - limit threshold setting pin. there is an internal source current 1 0 m a through a resistor from ocset pin to phase. this pin is used to monitor the voltage drop across the drain and source of the low - side mosfet for current - limit. 11 phase junction p oint of t he h igh - side mosfet source, o utput f ilter i nductor a nd t he l ow - side mosfet drain. connect this pin to the source of the high - side mosfet. phase serves as the lower supply rail for the u g high - side gate driver. 12 ugate output of the high - side mosfet driver. connect this pin to gate of the high - side mosfet. 13 boot supply input for t he ug ate driver a nd a n i nternal l evel - shift c ircuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. 14 rtn this pin is the negative node o f the differential remote voltage sensing. the rtn pin should be connected to the remote gnd sense point directly. 15 en enable pin of the pwm controller. when the en is above high logic level, the device is in automatic pfm/pwm mode. when the en is below low logic level, the device is in shutdown and only low leakage current is taken from v cc and v in . 16 ton this p in is a llowed to a djust t he s witching f requency. connect a resistor r ton =400k w ~ 1500k w from ton pin to v in .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 8 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 0 . 594 r e f e r e n c e v o l t a g e a c c u r a c y , v r e f ( v ) reference voltage accuracy vs . junction temperature - 50 - 30 10 50 110 130 150 90 30 - 10 junction temperature , t j ( o c ) 0 . 606 0 . 604 0 . 602 0 . 600 0 . 598 0 . 596 70 0 . 1 s w i t c h i n g f r e q u e n c y , f s w ( k h z ) switching frequency vs . converter output current 0 . 001 0 . 010 0 . 100 1 . 000 10 . 00 converter output current , i out ( a ) 1000 100 10 1 v in = 8 v , v out = 1 . 05 v 14 o c s e t s o u r c i n g c u r r e n t , i o c s e t ( m a ) ocset sourcing current vs . junction temperature - 50 - 30 10 50 90 110 150 70 30 - 10 130 26 24 22 20 18 16 junction temperature , t j ( o c ) 0 . 10 1 . 00 10 . 00 converter output current , i out ( a ) 0 10 e f f i c i e n c y ( % ) 70 80 90 60 50 100 40 30 20 efficiency vs load current v in = 8 v , v out = 1 . 05 v 0 . 01 100 . 00 h - side : sm 4370 x 1 l - side : sm 4373 x 1 0 . 10 1 . 00 10 . 00 0 10 e f f i c i e n c y ( % ) 70 80 90 60 50 100 40 30 20 0 . 01 100 . 00 converter output current , i out ( a ) efficiency vs load current v in = 19 v , v out = 1 . 05 v h - side : sm 4370 x 1 l - side : sm 4373 x 1 1 . 015 1 . 010 0 . 980 c o n v e r t e r o u t p u t v o l t a g e , v o u t ( v ) converter output current , i out ( a ) 3 1 . 020 1 . 005 1 . 000 0 . 995 0 . 990 0 . 985 4 5 6 v in = 8 v v in = 19 v converter output voltage vs . converter output current 2 7 8 9 10 external mode
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . enable at zero initial voltage of v out ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 500 m s / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc 1 2 3 4 enable before end of soft - stop 1 2 3 4 ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 500 m s / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc shutdown with soft - stop at no load 1 4 2 3 ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 10 ms / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc 1 4 2 3 ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 20 m s / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc shutdown at i out = 20 a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 0 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . 1 4 3 2 ch 2 : v lgate , 5 v / div , dc ch 3 : v out , 100 mv / div , ac time : 2 g s / div ch 1 : v phase , 20 v / div , dc ch 4 : il , 10 a / div , dc operating at pfm mode 1 4 2 3 ch 2 : v lgate , 5 v / div , dc ch 3 : v out , 100 mv / div , ac time : 2 g s / div ch 1 : v phase , 20 v / div , dc ch 4 : il , 10 a / div , dc operating at pwm mode il = 3 a over - current protection 1 4 2 3 ch 2 : v out , 1 v / div , dc ch 3 : v phase , 20 v / div , dc time : 20 g s / div ch 1 : v pok , 5 v / div , dc ch 4 : i l , 20 a / div , dc under - voltage protection 1 4 2 3 ch 2 : v ugate , 20 v / div , dc ch 3 : v lgate , 10 v / div , dc time : 10 g s / div ch 1 : v fb , 500 mv / div , dc ch 4 : v pok , 5 v / div , dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 1 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . 1 2 3 4 load transient 0 a - > 17 . 5 a - > 0 a when total i mpedance of line = 20 mohm ch 2 : v out _ remote , 200 mv / div , dc ch 3 : i out , 10 a / div , dc time : 20 g s / div ch 1 : v out _ near , 200 mv / div , dc ch 4 : v gnd _ near - remote , 200 mv / div , dc 1 2 3 4 ch 2 : v out _ remote , 200 mv / div , dc ch 3 : i out , 10 a / div , dc time : 20 g s / div ch 1 : v out _ near , 200 mv / div , dc ch 4 : v gnd _ near - remote , 200 mv / div , dc load transient 5 a - > 20 a - > 5 a when total i mpedance of line = 20 mohm ch 2 : v out _ remote , 200 mv / div , dc ch 3 : i l , 10 a / div , dc time : 2 g s / div ch 1 : v out _ near , 200 mv / div , dc ch 4 : v gnd _ near - remote , 200 mv / div , dc 1 2 4 3 remote sense when total i mpedance of line = 20 mohm
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 2 b l o c k d i a g r a m fb error comparator ov uv 70 % v ref 125 % v ref v ref por vcc en digital soft start / soft sop p w m s i g n a l c o n t r o l l e r v cc boot ugate phase lgate thermal shutdown gnd pok fault latch logic on - time generator v ref x 125 % z c phase debounce time v cc 10 m a v out v out ocp v rocset sense low - side vout rtn diffout diffout ocset pvcc pgn d frequency adjustable ton refin refin en 90 % v ref
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 3 t y p i c a l a p p l i c a t i o n c i r c u i t phase rtn gnd pvcc ocset vout apw 8728 ( tqfn 3 x 3 - 16 ) c in 10 m f x 2 l 1 0 . 5 h v in v out ugate c out 330 m f supply 5 v boot 9 5 14 1 8 11 r vc c 2 r 2 c pv cc 1 m f q 1 apm 4350 q 2 apm 4358 c boot 0 . 1 m f r ocse t c out mlcc 22 m fx 4 lgate l o a d 3 pok 4 r pok 100 k w v + _ near v - _ near v + _ remote v - _ remote refi n on off q 3 2 n 7002 dac source 6 ton fb en enable source 15 vcc 2 c v cc 1 m f pgnd 3 7 10 750 k 12 13 16 for external mode application phase rtn gnd pvcc ocset vout apw 8728 ( tqfn 3 x 3 - 16 ) c in 10 m f x 2 l 1 0 . 5 h v in v out ugate c out 330 m f supply 5 v boot 9 5 14 1 8 11 r vc c 2 r 2 c pv cc 1 m f q 1 apm 4350 q 2 apm 4358 c boot 0 . 1 f r ocset lgate 3 pok 4 r pok 100 k w refi n on off q 3 2 n 7002 dac source 6 ton fb en enable source 15 vcc 2 c v cc 1 m f pgnd 3 7 10 r top 10 k w r gnd 10 k w 750 k 12 13 16 for internal mode application
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n constant-on-time pwm controller with input feed-for- ward pulse-frequency modulation (pfm) the constant-on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. this ar- chitecture relies on the output filter capacitor?s effective series resistance (esr) to act as a current-sense resis- tor so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time is controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- tional to the input voltage and directly proportional to the output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block. the switching frequency control circuit senses the switch- ing frequency of the high-side switch and keeps regulat- ing it at a constant frequency in pwm mode. the design improves the frequency variation and is more outstand- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. both in pfm and pwm, the on-time generator, which senses input voltage on ton pin, provides very fast on-time response to input line transients. another one-shot sets a minimum off-time (typical: 450ns). the on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. in pfm mode, an automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: where f sw is the nominal switching frequency of the con- verter in pwm mode. the load current at handoff from pfm to pwm mode is given by: in out sw pfm on v v f 1 t = - in out sw out in pfm on out in ) pfmtopwm ( load v v f 1 l 2 v v t l v v 2 1 i - = - = - power-on-reset (por) a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising por voltage threshold (4.35v, typical), the por signal goes high and the chip initiates soft-start operations. when this voltage drops lower than 4.25v (typical), the por disables the chip. refin pin control the voltage (v refin ) applied to refin pin selects either enable-shutdown or adjustable external reference. when v refin is above the en high threshold (2.8v, typical), the pwm is enabled. when v refin is from 0.5v to 2.5v, the output voltage can be programmed as same as v refin voltage. when v refin is below the en low threshold, the chip is in the shutdown and only low leakage current is taken from vcc. once APW8728 has been operating at internal mode, it is unable to transform into external mode. on the other hand, it is able to transform into internal mode. the slew rate of v refin must be faster than 0.5v/ m s to avoid wrong output voltage.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 5 en pin control when v en is above the en high threshold (0.5v, minimum), the converter is enabled in automatic pfm/ pwm operation mode. when v en is below the en low threshold (0.4v, maximum), the chip is in the shutdown and only low leakage current is taken from vcc. f u n c t i o n d e s c r i p t i o n ( c o n t . ) d i g i t a l s o f t - s t a r t t h e a p w 8 7 2 8 i n t e g r a t e s d i g i t a l s o f t - s t a r t c i r c u i t s t o r a m p u p t h e o u t p u t v o l t a g e o f t h e c o n v e r t e r t o t h e p r o g r a m m e d r e g u l a t i o n s e t p o i n t a t a p r e d i c t a b l e s l e w r a t e . t h e s l e w r a t e o f o u t p u t v o l t a g e i s i n t e r n a l l y c o n t r o l l e d t o l i m i t t h e i n r u s h c u r r e n t t h r o u g h t h e o u t p u t c a p a c i t o r s d u r i n g s o f t - s t a r t p r o c e s s . t h e f i g u r e 1 s h o w s s o f t - s t a r t s e q u e n c e . w h e n t h e e n p i n i s p u l l e d a b o v e t h e r i s i n g e n t h r e s h o l d v o l t a g e , t h e d e v i c e i n i t i a t e s a s o f t - s t a r t p r o c e s s t o r a m p u p t h e o u t p u t v o l t a g e . t h e s o f t - s t a r t i n t e r v a l i s 1 m s ( t y p i c a l ) a n d i n d e p e n d e n t o f t h e u g a t e s w i t c h i n g f r e q u e n c y . vcc and pvcc refin en vout 1 ms v pok 1 . 6 ms f i g u r e 1 . s o f t - s t a r t s e q u e n c e during soft-start stage before the pok pin is ready, the under-voltage protection is prohibited. the over-voltage and current-limit protection functions are enabled. if the output capacitor has residue voltage before start-up, both low-side and high-side mosfets are in off-state until the internal digital soft-start voltage equals to the v fb voltage. this will ensure that the output voltage starts from its existing voltage level. in the event of under-voltage, over-voltage, over- power ok indicator the APW8728 features an open-drain pok pin to indi- cate output regulation status. in normal operation, when the output voltage rises 90% of its target value, the pok goes high after 63 m s internal delay. when the output volt- age outruns 70% or 125% of the target voltage, pok sig- nal will be pulled low immediately. since the fb pin is used for both feedback and monitor- ing purposes, the output voltage deviation can be coupled directly to the fb pin by the capacitor in parallel with the voltage divider as shown in the typical applications. in order to prevent false pok from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. under-voltage protection (uvp) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- ger than current-limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the fb volt- age after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under- voltage threshold, the under-voltage threshold is 70% of the nominal output voltage, the internal uvp delay counter starts to count. after 16 m s debounce time, the device turns off both high-side and low-side mosefet with latched and starts a soft-stop process to shut down the output gradually. toggling enable pin to low or recycling pvcc or vcc, will clear the latch and bring the chip back to operation. o v e r - v o l t a g e p r o t e c t i o n ( o v p ) the over-voltage protection monitors the fb voltage to prevent the output from over-voltage condition. when the output voltage rises above 125% of the nominal output voltage, the APW8728 turns off the high-side mosfet and turns on the low-side mosfet until the output volt- age falls below the falling ovp threshold. temperature, or shutdown, the chip enables the soft-stop function. the soft-stop function discharges the output voltages to the pgnd through an internal 20 w switch.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 2 . c u r r e n t - l i m i t a l g o r i t h m c u r r e n t - l i m i t the current-limit circuit employs a ?valley? current-sens- ing algorithm (see figure 2). the APW8728 uses the low-side mosfet?s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at phase pin is above the current- limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the current- limit threshold by an amount equals to the inductor ripple 4 current. therefore, the exact current-limit characteristic and maximum load capability are the functions of the sense resistance, inductor value, and input voltage. time i n d u c t o r c u r r e n t , i l 0 i out i peak i limit d i the pwm controller uses the low-side mosfets on-re- sistance r ds(on) to monitor the current for protection against shortened outputs. the mosfet?s r ds(on) is var- ied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacture?s datasheet. when lg is turned on, the ocset pin can source 20 m a where r ocset is the resistor of current-limit setting threshold. r ds(on) is the low side mosfets conducive resistance. i limit is the setting current-limit threshold. i limit can be expressed as i out minus half of peak-to-peak in- ductor current. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at phase. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when com- bined with the under-voltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. over-temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over- temperature protection state that suspends the pwm, which forces the ugate and lgate gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 25 o c. the otp is designed with a 25 o c hysteresis to lower the average t j during continuous thermal overload conditions, which in- creases lifetime of the APW8728. p r o g r a m m i n g t h e o n - t i m e c o n t r o l a n d p w m s w i t c h - i n g f r e q u e n c y t h e a p w 8 2 8 d o e s n o t u s e a c l o c k s i g n a l t o p r o d u c e p w m . t h e d e v i c e u s e s t h e c o n s t a n t - o n - t i m e c o n t r o l a r c h i t e c - t u r e t o p r o d u c e p s e u d o - f i x e d f r e q u e n c y w i t h i n p u t v o l t a g e f e e d - f o r w a r d . t h e o n - t i m e p u l s e w i d t h i s p r o p o r t i o n a l t o o u t p u t v o l t a g e v o u t a n d i n v e r s e s p r o p o r t i o n a l t o i n p u t v o l t - a g e v i n . i n p w m , t h e o n - t i m e c a l c u l a t i o n i s w r i t t e n a s b e - l o w : ? ? = - in ton on v r t out v 10 4 12 through an external resistor for adjusting current-limit threshold. the voltage at ocset pin is equal to v phase +20 m a x r ocset . the relationship between the sampled voltage v ocset and the current-limit threshold i limit is given by: 20 m a x r ocset = i limit x r ds(on) w h e r e : r t o n i s t h e r e s i s t o r c o n n e c t e d f r o m t o n p i n t o p h a s e p i n . f u r t h e r m o r e , t h e a p p r o x i m a t e p w m s w i t c h i n g f r e - q u e n c y i s w r i t t e n a s :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 7 f u n c t i o n d e s c r i p t i o n ( c o n t . ) p r o g r a m m i n g t h e o n - t i m e c o n t r o l a n d p w m s w i t c h - i n g f r e q u e n c y ( c o n t . ) on in out sw sw on t v v f f t = t = d where: f sw is the pwm switching frequency. APW8728 doesn?t have vin pin to calculate on-time pulse width. therefore, monitoring v ton voltage as input voltage to calculate on-time. and then, use the relationship be- tween ontime and duty cycle to obtain the switching frequency. the curve below is the relationship between r ton and the switching frequency f sw . r o m o t e s e n s e APW8728 has a rtn pin for external mode applications that require remote sense. in some applications where high current, low voltage and accurate output voltage regu- lation are needed, rtn can sense the negative terminal of remote load capacitor directly, and improve output volt- age drop which is due to the board interconnection loss.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 8 a p p l i c a t i o n i n f o r m a t i o n o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t a g e i s f i x e d , i t c a n b e w r i t t e n a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t p u t c a p a c i t o r s e l e c t i o n the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient reponse. higher inductor value reduces the inductor?s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d o u t p u t v o l t a g e s e t t i n g w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t h o u g h t h e i n d u c t o r v a l u e a n d f r e q u e n c y a r e i n c r e a s e d a n d t h e r i p p l e c u r r e n t a n d v o l t a g e a r e r e d u c e d , a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u - l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this results in a larger output ripple voltage. besides, the inductor needs to have low dcr to reduce the loss of efficiency. o u tp ut voltage ripple and the transient volta ge devia- tion are factors which have to be taken into con sider- ation when selecting an output capacitor. higher capaci- tor value and lower esr reduce the out put ripple and the load transient drop. therefore, selecting high per- formance low esr capacitors is recommended for switching regulator applications. in addition to h igh frequency noise related to mosfet turn-on and turn - o ff, the output voltage ripple includes the capaci tance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor?s current. t h e s e t w o v o l t a g e s c a n b e r e p r e s e n t e d b y : these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. a small decoupling capacitor (1 m f) in parallel for bypass- ing the noise is also recommended, and the voltage rat- ing of the output capacitors are also must be considered. to support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating. ? ? ? ? ? + = gnd top out r r 1 0.6 v i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s where 0.6 is the reference voltage, r top is the resistor connected from converter?s output to fb, and r gnd is the resistor connected from fb to gnd. suggested r gnd is in the range from 1k to 20k w . to prevent stray pickup, locate resistors r top and r gnd close to APW8728. similarly, when v refin is from 0.5v to 2.5v, the output voltage can be programmed as same as v refin voltage. the output voltage is adjustable from 0.6v to 3.3v with a resistor-divider connected with fb, gnd, and converter?s output. the voltage (v refin ) applied to refin pin selects adjustable external reference from 0.5v to 2.5v. using 1% or better resistors for the resistor-divider is recommended. the output voltage is determined by:
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 1 9 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) i n p u t c a p a c i t o r s e l e c t i o n ( c o n t . ) m o s f e t s e l e c t i o n t h e a p p l i c a t i o n f o r a n o t e b o o k b a t t e r y w i t h a m a x i m u m v o l t a g e o f 2 4 v , a t l e a s t a m i n i m u m 3 0 v m o s f e t s s h o u l d b e u s e d . t h e d e s i g n h a s t o t r a d e o f f t h e g a t e c h a r g e w i t h t h e r ds(on) o f t h e m o s f e t : t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r a n s f e r c a p a c i - t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) l a y o u t c o n s i d e r a t i o n i n a n y h i g h s w i t c h i n g f r e q u e n c y c o n v e r t e r , a c o r r e c t l a y o u t i s i m p o r t a n t t o e n s u r e p r o p e r o p e r a t i o n o f t h e r e g u l a t o r . w i t h p o w e r d e v i c e s s w i t c h i n g a t h i g h e r f r e q u e n c y , t h e r e s u l t i n g c u r r e n t t r a n s i e n t w i l l c a u s e v o l t a g e s p i k e a c r o s s t h e i n t e r c o n n e c t i n g i m p e d a n c e a n d p a r a s i t i c c i r c u i t e l e m e n t s . a s a n e x a m p l e , c o n s i d e r t h e t u r n - o f f t r a n s i t i o n o f t h e p w m m o s f e t . b e f o r e t u r n - o f f c o n d i t i o n , t h e m o s f e t i s c a r r y i n g t h e f u l l l o a d c u r r e n t . d u r i n g t u r n - o f f , c u r r e n t s t o p s f l o w i n g i n t h e m o s f e t a n d i s f r e e w h e e l i n g b y t h e l o w s i d e m o s f e t a n d p a r a s i t i c d i o d e . a n y p a r a s i t i c i n d u c t a n c e o f t h e c i r c u i t g e n e r a t e s a l a r g e v o l t a g e s p i k e d u r i n g t h e s w i t c h i n g i n t e r v a l . i n g e n e r a l , u s i n g s h o r t a n d w i d e p r i n t e d c i r c u i t t r a c e s s h o u l d m i n i m i z e i n t e r c o n n e c t - i n g i m p e d a n c e s a n d t h e m a g n i t u d e o f v o l t a g e s p i k e . b e s i d e s , s i g n a l a n d p o w e r g r o u n d s a r e t o b e k e p t s e p a - r a t i n g a n d f i n a l l y c o m b i n e d u s i n g g r o u n d p l a n e c o n s t r u c - t i o n o r s i n g l e p o i n t g r o u n d i n g . t h e b e s t t i e - p o i n t b e t w e e n the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. below is a checklist for your layout: f o r t h e l o w - s i d e m o s f e t , b e f o r e i t i s t u r n e d o n , t h e b o d y d i o d e h a s b e e n c o n d u c t i n g . t h e l o w - s i d e m o s f e t d r i v e r w i l l n o t c h a r g e t h e m i l l e r c a p a c i t o r o f t h i s m o s f e t . i n t h e t u r n i n g o f f p r o c e s s o f t h e l o w - s i d e m o s f e t , t h e l o a d c u r r e n t w i l l s h i f t t o t h e b o d y d i o d e f i r s t . t h e h i g h d v / d t o f t h e p h a s e n o d e v o l t a g e w i l l c h a r g e t h e m i l l e r c a p a c i - t o r t h r o u g h t h e l o w - s i d e m o s f e t d r i v e r s i n k i n g c u r r e n t p a t h . t h i s r e s u l t s i n m u c h l e s s s w i t c h i n g l o s s o f t h e l o w - s i d e m o s f e t s . t h e d u t y c y c l e i s o f t e n v e r y s m a l l i n h i g h b a t t e r y v o l t a g e a p p l i c a t i o n s , a n d t h e l o w - s i d e m o s f e t w i l l c o n d u c t m o s t o f t h e s w i t c h i n g c y c l e ; t h e r e f o r e , when using smaller r ds(on) of the low-side mosfet, the con- verter can reduce power loss. t h e g a t e c h a r g e f o r t h i s m o s f e t i s u s u a l l y t h e s e c o n d a r y c o n s i d e r a t i o n . t h e h i g h - s i d e m o s f e t d o e s n o t h a v e t h i s z e r o v o l t a g e s w i t c h - i n g c o n d i t i o n ; i n a d d i t i o n , i t c o n d u c t s f o r l e s s t i m e c o m - p a r e d t o t h e l o w - s i d e m o s f e t , s o t h e s w i t c h i n g l o s s t e n d s t o b e d o m i n a n t . p r i o r i t y s h o u l d b e g i v e n t o t h e m o s f e t s w i t h l e s s g a t e c h a r g e , s o t h a t b o t h t h e g a t e d r i v e r l o s s a n d s w i t c h i n g l o s s w i l l b e m i n i m i z e d . where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high- side mosfet includes an additional transi tion loss. t he switching interval , t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. temperature? curve of the power mosfet. h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r - u p , t h e i n p u t c a p a c i t o r s h a v e t o h a n d l e g r e a t a m o u n t o f s u r g e c u r r e n t . f o r l o w - d u t y n o t e b o o k a p p l i a c t i o n s , c e r a m i c c a p a c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e a d a n c e p c b l a y o u t . k e e p t h e s w i t c h i n g n o d e s ( u g a t e , l g a t e , b o o t , a n d p h a s e ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 0 locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can?t be close to the switching signal traces (ugate, lgate, boot, and phase). a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t c o n s i d e r a t i o n ( c o n t . ) t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t w i t h h i g h p e a k c h a r g i n g a n d d i s c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e a n d l g a t e ) s h o u l d b e s h o r t a n d w i d e . p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e - t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . i n a d d i t i o n , t h e l a r g e l a y o u t p l a n e b e t w e e n t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e n o d e s ) c a n g e t b e t t e r h e a t s i n k i n g . the pgnd is the current sensing circuit reference ground and also the power ground of the lgate low- side mosfet. on the other hand, the pgnd trace should be a separate trace and independently go to the source of the low-side mosfet. besides, the cur- rent sense resistor should be close to ocset pin to avoid parasitic capacitor effect and noise coupling. d e c o u p l i n g c a p a c i t o r s , t h e r e s i s t o r - d i v i d e r , a n d b o o t c a p a c i t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . ) t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i - t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i - t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . p o s s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l l e l w i t h t h e s e s t r a c e s o n a n y l a y e r . 0 . 5 mm 0 . 24 mm 0 . 508 mm 0 . 162 mm 1 . 66 mm 3 mm * just recommend 3 mm 1 . 6 6 m m 0 . 5 mm * r e c o m m e n d e d m i n i m u m f o o t p r i n t
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 1 p a c k a g e i n f o r m a t i o n t q f n 3 x 3 - 1 6 d e pin 1 a b a1 a3 d2 e 2 e pin 1 corner k l note : follow jedec mo-220 weed-4. s y m b o l min. max. 0.80 0.00 0.18 0.30 1.50 1.80 0.05 1.50 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tqfn3x3-16 0.30 0.50 1.80 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.059 0.071 0.059 0.012 0.020 0.70 0.071 0.028 0.002 0.50 bsc 0.020 bsc k 0.20 0.008 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 2 application a h t1 c d d w e1 f 330 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tqfn3x3 - 16 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0 .40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d d e v i c e s p e r u n i t package type unit quantity tqfn3x3 - 16 tape & reel 3000
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 3 c l a s s i f i c a t i o n p r o f i l e t a p i n g d i r e c t i o n i n f o r m a t i o n t q f n 3 x 3 - 1 6 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 4 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spe cified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - d e c . , 2 0 1 2 a p w 8 7 2 8 w w w . a n p e c . c o m . t w 2 5 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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